The present invention relates to microelectronic device fabrication methods, in particular, to methods for fabricating interconnections including a contact hole and an interconnection line in microelectronic devices.
When forming an interconnection to a microelectronic layer of a microelectronic device, a contact hole typically is formed in an insulating layer covering the microelectronic layer, and the contact hole is filled with a conductive material to form an interconnection. Several techniques have been developed for filling contact holes, including widely-used selective tungsten, blanket tungsten, laser reflow, high temperature deposition, and aluminum reflow processes. As the density of the integration of microelectronic devices has increased, however, the cross-sectional area of contact holes used for interconnections has generally decreased, leading to a need to use contact holes having increased aspect ratio. It may be difficult to fill such high aspect ratio contact holes using conventional techniques.
Long throw sputtering (LTS) and high-pressure reflow processes have been developed for filling high aspect ratio contact holes. In the LTS process, improved step coverage, and thus improved contact hole filling capability, may be achieved by increasing the distance between a target and a wafer to be processed for improving an initial step coverage of the contact hole. However, a void may be formed due to reduced deposition speed of the sputtered conductive material and asymmetry between the edge and the center of the contact hole where the conductive material is deposited. Such problems may make it difficult to fill a contact hole having an aspect ratio of 4 or greater.
High-pressure reflow processes typically involve deposition of aluminum on a contact hole, and subsequent treatment under high temperature and pressure, for example, 400xc2x0 C. and 600 MPa, to reflow the deposited material into the contact hole. However, although the conventional high temperature reflow processes may be effective for filling contact holes having an aspect ratio of 10 or greater, they may not be effective for filling large diameter contact holes.
FIGS. 1A and 1B are cross-sectional views illustrating conventional techniques of forming an interconnection according to the prior art. Referring to FIGS. 1A and 1B, a contact hole is formed in an insulating layer 12 on a microelectronic substrate 10 using, for example, a photolithography process. The contact hole is then cleaned using a hydrogen fluoride, and a barrier layer 14 and an aluminum layer 16 are deposited on the resultant structure. The deposited aluminum is then reflowed by applying high temperature and pressure, for example, 400xc2x0 C. and 600 MP, which causes the deposited aluminum to fill the contact hole as illustrated in FIG. 1B.
As described above, although the conventional high temperature reflow processes may be effective for filling contact holes having an aspect ratio of 10 or greater, it may not be effective for filling large diameter contact holes. That is, if there is a failure to bridge a large contact hole, this may lead to the generation of a void A in the contact hole during the reflow process as shown in FIG. 1B. In addition, if there are a plurality of contact holes having different contact sizes in the same layer, it is more difficult to fill the contact holes without the generation of voids.
FIGS. 5A to 5C are cross-sectional views illustrating a conventional aluminum reflow technique for forming an interconnection when a plurality of contact holes having different contact sizes are formed in the same insulation layer. Referring to FIG. 5A, an insulation layer 62 is formed on a substrate 60 having a planarized surface. A plurality of contact holes 64a and 64b are formed in the insulation layer 62 by a general photolithography technique. The contact hole 64a has a contact diameter of xe2x80x9caxe2x80x9d and the other contact hole 64b has a contact diameter of xe2x80x9cbxe2x80x9d which is larger than a contact size of xe2x80x9caxe2x80x9d. Then, an aluminum layer 66 is deposited on the exposed surface of the substrate 60 and the insulation layer 62 with a thickness of xe2x80x9cT1xe2x80x9d.
Referring to FIG. 5B, a conventional aluminum reflow process is performed on the resultant structure of FIG. 5A by supplying heat. At this time, the aluminum layer 66 is flowed into the plurality of contact holes 64a and 64b, but the relatively small contact hole 64a may include a void 67 and the relatively large contact hole 64b may be not fully filled with the aluminum.
Referring to FIG. 5C, a Chemical-Mechanical Polishing(CMP) process is performed on the resultant structure for planarization, to expose the insulation layer 62. At this time, although the surface of the small contact hole 64a is planarized, the large contact hole 64b is not sufficiently planarized.
In the meantime, in the above aluminum reflow process, if the thickness T1 of the deposited aluminum is controlled on the basis of the large contact hole 64b, the thickness of the aluminum layer to be deposited is increased, to thereby bridge the aluminum layer 66 at the upper portion of the small contact hole 64a. Therefore, in a subsequent reflow process, a void is formed in the small contact hole 64a. This void also acts as a factor of deterioration of device.
For multi-layered microelectronic devices, the aspect ratio of contact holes may be even further increased, causing problems such as a non-planarization of interconnection layers, inferior step coverage, metal shorts, low yields, and reduced reliability. In order to address many of these problems, damascene techniques have been developed.
FIG. 2 is a cross-sectional view of a conventional dual damascene structure. The dual damascene structure includes a stud (contact hole) connected to the underlying substrate 10 and an interconnection line with a predetermined depth in the insulation layer 12. If the stud is located apart from a center of the interconnection line, the dual damascene structure has substantially asymmetrical characteristics for filling with a material. In the meanwhile, if the stud is located in a center of the interconnection lines, the dual damascene structure has also asymmetrical characteristics for filling due to the differences of width and depth between the stud and the interconnection lines. These damascene techniques typically involve etching a planar insulating layer to form a via, filling the via with metal 18, and removing excessive metal overlying the insulating layer using chemical mechanical polishing (CMP). Sputtered aluminum or tungsten deposited by chemical vapor deposition (CVD) are commonly used as the filling metal.
For CVD-deposited tungsten, a titanium nitride layer may be used as an adhesion layer, and the adhesion layer lifted by tungsten fluoride (WF6) gas. However, during planarization using CMP, a defect may be formed in the metal fill due to a seam which is typically formed during chemical vapor deposition of tungsten. For sputtered aluminum, the contact hole may not be fully filled due to an inferiority of step coverage, typical of the sputtering process. This may resulting in the formation of a void B, as illustrated in FIG. 2.
In light of the foregoing, it is an object of the present invention to provide improved methods for forming interconnections including a contact hole and an interconnection line in microelectronic devices which reduce the probability of voids and other defects.
It is another object of the present invention to provide methods for forming an interconnections in microelectronic devices which are suitable for use with large contact holes.
It is still another object of the present invention to provide methods for forming a contact holes in microelectronic devices which are suitable for use with a plurality of contact holes having a different contact size.
It is yet still another object of the present invention to provide methods for forming interconnection lines in microelectronic devices which are suitable for use with a plurality of interconnection lines having a different widths.
It is yet still another object of the present invention to provide methods for forming interconnections including a stud and an interconnection line in microelectronic devices which are suitable for use with an asymmetrical characteristic for filling.
These and other objects features and advantage are provided according to a first aspect of the present invention by methods for forming an interconnection to a microelectronic layer in which a plurality of contact holes are formed through an insulation layer covering the microelectronic layer, wherein at least one contact hole out of the contact holes has a different contact size from the others. Then, conductive material is formed on the insulation layer and in the contact holes to a predetermined thickness such that the conductive material bridges a largest contact hole of the contact holes at the upper side of the largest contact hole, forming a void therein. After this, the conductive material is reflowed to thereby fill the contact holes, by supplying a high pressure such that at least the void formed in the largest contact hole is filled, and to form an interconnecting conductive region extending from the surface of the insulation layer to the microelectronic layer.
Preferably, a step of forming a barrier metal layer on the exposed surface of the contact holes is performed before the step of forming the conductive material. A step of planarizing the reflowed conductive material to remove the conductive material overlying the surface of the insulation layer is preferably performed, after the step of reflowing the conductive material to thereby expose the insulation layer.
According to a second aspect of the present invention, a method of fabricating an interconnection to an underlying microelectronic layer includes removing a portion of the insulation layer to form at least one asymmetrical structure therethrough and thereby expose a portion of the underlying microelectronic layer, wherein the asymmetrical structure has an asymmetrical characteristics for filling a subsequent conductive material. Then, a conductive material is formed on the insulation layer and in the asymmetrical structure with a predetermined thickness such that at least the conductive material bridges the asymmetrical structure at the upper end of the structure. The conductive material is then reflowed to thereby fill the asymmetrical structures, by supplying a high pressure such that voids formed in the asymmetrical structure disappear.
Preferably, the asymmetrical contact hole is a dual damascene structure which is a combination of an interconnection line with a predetermined depth in the insulation layer and a stud, which is overlapped by the interconnection line and connected to the underlying microelectronic layer.
According to a third aspect of the present invention, a method of fabricating an interconnection to a microelectronic layer in a substrate includes forming a first insulation layer on the substrate, covering the microelectronic layer, the first insulation layer having a surface opposite the microelectronic layer. A second insulation layer is formed on the substrate, covering the first insulation layer. Portions of the first and second insulation layers are then removed to form a contact hole therethrough and expose a portion of the microelectronic layer, leaving portions of the second insulation layer extending past the first insulation layer at peripheral portions of the contact hole, overhanging the exposed portion of the microelectronic layer. A conductive material is deposited on the substrate, bridging the contact hole at the portions of the second insulation layer extending past the first insulation layer. The deposited conductive material is then reflowed to thereby fill the contact hole, by supplying a high pressure such that a void formed in the contact hole is filled, forming a conductive region extending from the surface of the first insulation layer to the microelectronic layer.
Preferably, the first insulation layer and the second insulation layers have first and second etching rates, respectively, with respect to an etchant, the second etching rate preferably being less than the first etching rate. The contact hole preferably is formed by etching with the etchant to leave portions of the second insulation extending past the first insulation layer at peripheral portions of the contact hole, overhanging the exposed portion of the microelectronic layer. For example, the etchant may be hydrogen fluoride, the first insulation layer may include one of borophosphosilicate glass (BSPG) and undoped silicate glass (USG), and the second insulation layer may include one of silicon nitride and plasma-enhanced silane.
Prior to formation of the contact hole, a third insulation layer may be formed on second insulation layer. Then, portions of the first, second and third insulation layers may be removed to form a contact hole therethrough, exposing a portion of the active layer, and to leave portions of the second insulation layer extending past the first insulation layer at peripheral portions of the contact hole, overhanging the exposed portion of the microelectronic layer. The third insulation layer may be formed from the same type of material as the first insulation layer, and preferably is thinner than the first insulation layer.
The conductive material preferably includes one of aluminum or aluminum alloy, and the deposition preferably occurs by sputtering or Chemical Vapor Deposition method. Prior to depositing the conductive material, a barrier metal layer may be formed on the substrate, the barrier metal layer preferably including one of titanium and titanium nitride. Improved methods of forming interconnections are thereby provided.